A study on performances of carrier-based pulse-widthmodulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs

Use your smartphone to scan this QR code and download this article ABSTRACT Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages comparedwith traditional two level VSI. Among various types ofmultilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies requiremore semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter efficiency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated inMATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm.


INTRODUCTION
Multilevel inverters (MLIs) have been being researched for nearly forty years since the first introduction of three-level neutral-point-clamped (3L NPC) voltage source inverter (VSI) in 1981 1,2 . Compared with traditional two-level VSI (2L VSI), 3L NPC VSI offers a larger number of benefits. For instance, 3L NPC VSI has lower distortion of output voltage and dv/dt, lower distortion of input current, smaller magnitude of common-mode voltage (CMV) or even elimination of CMV by using some sophisticated modulation methods, and ability in operation with a lower switching frequency [1][2][3][4][5][6][7] . Among with many types of 3L NPC topology, 3L T-type NPC (3L TNPC) topology has an advantage in terms of efficiency compared to 3L NPC 5 . For example, 3L TNPC VSI possesses higher efficiency in low-voltage applications for the switching frequency between 4-25 kHz such as photovoltaic (PV) system, uninterruptible power supplies (UPSs), and automotive converter system 5,8,9 . 3L TNPC VSI combines the benefits of both 2L VSI and 3L NPC VSI, such as lower conduction losses, lower switching losses and higher output power quality 8 . The TNPC topology also allows the usage of lower voltage rating power switches and offers considerably power losses compared with that of NPC topology 5,8 . However, due to the use of total 12 power switches topology, the reliability of 3L TNPC VSI inverter is an important issue which is related to the cost and efficiency of the overall system 8 . It is summarized that there are two typical types of failure that may occur in semiconductor switches in a power inverter, which are switch-short-circuit (SSC) fault and switch-opencircuit (SOC) fault, respectively [8][9][10] . SSC faults often come from the over-voltage, over-current, avalanched stress or over-thermal issues, which could result in serious damage to the switching devices due to the abnormal overcurrent 8,9 . Typically, the inverters stop operation after the detection of SSC fault for safety reason 10 . In contrast, SOC faults occur due to malfunction of gate driver circuits or the lifting of bonding wire caused by thermal cycling [8][9][10] . Although SOC faults do not lead to serious damage to the inverter compared with SSC faults, the system performance will deteriorate in SOC fault. In addition, SOC fault leads to current distortion of output, secondary issues in other components in the topology such as gate drivers and other IGBTs by means of noise and vibration 8 . The asymmetrical and distorted current caused by SOC fault may saturate transformer, trigger circuit protection 10 . Moreover, SOC faults could reduce the fundamental component of output voltage which is not allowed in certain voltage-sensitive applications, for example, UPS of PV systems 11 . Therefore, a modulation algorithm for 333-type VSI working under SOC faults should be developed to guarantee the desired fundamental component of output voltages as well as the balanced output currents. show that under SOC fault on one neutral-pointconnected leg and two neutral-point-connected legs, respectively. The topology in Figure 1(b) is called 332type VSI while that in Figure 1(c) is 322-type VSI. Certain studies on pulse-width modulation (PWM) techniques implemented on 333-type VSI under SOC fault conditions on neutral-point-connected legs were carried out at [8][9][10][11] . Study conducted by U. Choi et al. 8 proposed a diagnosis and tolerant algorithm for SOC fault considering two types of SOC fault which occurring in neural-point-connected bridge and in the main bridge. In case of SOC fault on neutral-pointconnected leg, the proposed technique in this study was based on SVPWM algorithm and had the capability in elimination of harmonic distortion in output current 8 resulting more reliability in 333-type VSI which could be implemented in servo and PV systems. Besides, this solution did not require any additional switches. S. Xu et al. investigated a faulttolerant topology and control strategy of 333-type VSI under different fault conditions including SOC faults on neutral-point-connected switch with ridethrough capability as well as maintained high-quality output 9 . However, this solution required a fourth redundant leg which could increase the system cost and power losses. Similarly, the solution proposed by J. He et al. 10 also used a redundant phase-leg yet utilized advanced switching techniques such as zero-voltage switching (ZVS) and zero-current switching (ZCS), thus relieved the thermal stress on switches and improved system efficiency while maintain the desired output voltage and output power. On the other hand, a carrier-based PWM (CBPWM) algorithm was de-veloped by T. Lee et al. 11 under SOC fault by transiting from three-level to two-level switching, thus keep the output voltage at the same rating value as the prefault condition. Despite the fact that two-level switching leads to an increment of harmonic distortion in output voltages, the reliability of the VSI in certain safety-critical applications has a higher priority 10,11 . Compared with other PWM techniques, for examples, space vector PWM (SVPWM), CBPWM is the highly popular algorithm which is based on the comparison of sinusoidal reference signals with carrier waves, thus make the modulation scheme easier to be implemented 10 . Thus, the implementation of CBPWM for 322-type VSI should be an attractive solution. Therefore, CBPWM algorithm will be developed in this paper. The main contents of this paper include three parts. Firstly, switching states and voltage vectors of the 322-type VSI are presented. Secondly, the principles of the proposed 322-CBPWM techniques including 322-SPWM and 322-MOCBPWM techniques are analyzed. Finally, simulation in MATLAB/Simulink and experimental implementation are carried out, giving the results for discussion and evaluation.

SWITCHING STATES AND OUTPUT VOLTAGES OF 322-TYPE VSI Switching States
Considering a 322-type VSI in Figure 1(c), the switching states will be described as following: For convenience in analysis, the phase-leg switching states set {S A , S B , S C } is used, which is defined as: Where The synthesized voltage vector in the stationary αβ coordinate system corresponding to each switching set {S A , S B , S C } is defined as 12 : where a = e j2π/3 . Table 1 lists available switching states of 322-type VSI and the corresponding synthesized output voltage vectors, which are then illustrated in Figure 2.
The space vector diagram has total of 12 vectors, which generate 11 different output voltages. There are 6 large vectors, named v14, v16, v18, v20, v22, and v24, respectively, which located at the large hexagon of 3L TNPC VSI. Each large vector has the magnitude of (2/3)V dc . Two medium vectors are v17 and v23 which locate in the β -axis and have a magnitude of Two small vectors are v1 and v11 which locate at the small hexagon according to 2L VSI and in the α-axis, each has the magnitude of (1/3)V dc . Two zero vectors v 0 and v 26 are both located at the hexagonal center.

Output voltages
The instantaneous phase-leg voltages are described by the following equations: The average value of each phase-leg voltage can be determined by the corresponding control voltage For them, the corresponding control voltages can be determined:

Considering a load voltage vector
where V m is the voltage magnitude and θ is the phase angle, respectively, the principle of 322-CBPWM technique to synthesize − → V t includes two steps. The first one is determining three control voltages {vdkA,vdkB,vdkC}. The second one uses these signals to implement carrier wave techniques, thus determining the switching states for each switch of the 322-type VSI.

Voltage modeling of inverter
Three-phase load voltages can be defined as: The analysis of 322-CBPWM is achieved by an average voltage model, as shown in Figure 3.
In general, the offset voltage value is in a range between two limitations, the minimum value V o f f min and the maximum value V o f f max , respectively: From load phase voltages calculated in (6), their maximum and minimum values can be obtained: Various modulation techniques can be proposed depending on the selected V o f f , . In 322-sinusoidal PWM (322-SPWM) technique, V o f f is determined by the following expression: In medium offset 322-CBPWM (322-MOCBPWM) technique, the value of V o f f is determined by: (12) or (13), three control signals {v dkA , v dkB , v dkC } can be determined by (6).

Carrier-based implementation
In this step, three control voltages are compared with the corresponding triangular-form carrier waves. Due to the reason that SOC fault occurs on the neutral-point-connected legs of phase B and C, the carrier waves of these phases must be changed to twolevel mode whereas phase A still works in three-level mode. Therefore, there are two carrier waveforms needed for phase A, which are v car1 with the magnitude between 1 and 2, and v car2 with the magnitude between 0 and 1, respectively. For the phase-leg B and C, there is only one carrier wave v car needed with the magnitude between 0 and 2.
The switching states and modulating signals are described in the following expressions: The switching states of each switch and instantaneous output phase-leg voltages of 322-type VSI in one sampling carrier cycle are illustrated in Figure 4. The algorithm in the proposed 322-SPWM and 322-MOCBPWM techniques is illustrated in Figure 5.

Modulation index definition
In this study, the modulation index is defined by the following expression: where V t(1) is the fundamental magnitude of phase load voltage, and V dc / √ 3 is the maximum fundamental magnitude of phase load voltage. In linear modulation, the limit of modulation index is 0≤m≤0.866 for 322-SPWM and 0≤m≤1 for 322-MOCBPWM, respectively.

Total harmonic distortion and weightedtotal harmonic distortion definitions
The Fourier series of a given periodical voltage v(t) can be written as follows: where Total harmonic distortion (THD) is usually used to evaluate the quality of a periodical signal. Its definition is 13 : The weighted-total harmonic distortion (WTHD) is defined by the following equation 13 : where V (1) is the magnitude of fundamental component of v(t).

RESULTS AND DISCUSSIONS
Two proposed techniques, i.e. 322-SPWM and 322-MOCBPWM, are firstly simulated by a MAT-LAB/Simulink model as shown in Figure 6, and secondly implemented on an experiment setup, as shown in Figure 7. Control card TI TMSF28377D is used as the main controller while the 322-type VSI is built from IGBTs STGW40N120KD and diodes STTH3012. Voltages and currents waveforms are measured by the digital oscilloscope Tektronix TDS 2024C. The simulation and experimental parameters are listed in Table 2.
Simulation and experiment results of 322-SPWM technique are presented in figures from Figure 8 to  Figure 12 while those of 322-MOCBPWM technique are illustrated in Figure 13 to Figure 17. Figure 8 shows the simulated output voltages and currents of 333-type VSI under different operating modes while Figure 9 shows the experiment results of output signals in the 322-type VSI working with the proposed 322-SPWM algorithm. The simulated spectrum analysis results of voltages are presented in Figure 10.
It is clear that under simultaneous SOC fault on phase B and phase C which makes the 333-type VSI become a 322-type one, there are not only distorted output voltages v AB , v BC , and v CA but also distorted and unbalanced currents i A , i B , and i C as shown in Figure 8(b). However, the proposed 322-SPWM technique improves voltages and current waveforms as shown in Fig 8(c). Experiment results in Figure 9 show the effectiveness of 322-SPWM. However, there are some differences between the experiment values compared to simulation ones. As an example, with the proposed 322-SPWM, THD(v A3B2 ) in simulation is 42.5% obtained from Figure 10(c) while the corresponding experiment value is 47.0% as shown in Figure 9(a). In terms of WTHD value, the experiment one is higher than that in simulation (0.88% compared to 0.37%). The effectiveness of the proposed technique in simulation can be obtained from the spectrum analysis results in Figure 10. For instance, in terms of v AB , in normal condition (333-type VSI with conventional SPWM or 333-SPWM), Figure 10    In addition, the THD and WTHD values are also improved: Figure 10(c) shows that THD(v A3B2 )=42.5% and WTHD(v A3B2 )=0.37% while those are 68.9% and 8.61%, respectively, in the faulty condition. It is also seen that THD(v A3B2 ) is higher than THD(v A3B3 ) by 73% and WTHD(v A3B2 ) is higher than WTHD(v A3B3 ) by 85%.
Due to the fact that in the 322-type VSI, both L2L voltages v AB and v CA are measured between a 3L phase-leg and a 2L phase-leg, the effectiveness of proposed 322-SPWM technique in improvement harmonics distortion of v CA are the same as those of v AB . However, the L2L voltage v BC is the worst case under SOC fault condition. Spectrum analysis in Figure 10(b) shows that under faulty condition, the fundamental magnitude value V B2C2_0 =55.7 V, causing a reduction of 30% compared with that in prefault operation. The harmonic distortion metrics are THD(v B2C2_0 )=83.0% and WTHD(v B2C2_0 )=7.54% while those values corresponding to normal operation are THD(v B3C3 )=24.5% and WTHD(v B3C3 )=0.20%, respectively, as shown in Figure 10(a). The proposed 322-SPWM technique provides not only the fundamental component of 80 V as same as pre-fault condition, but also the reduced THD and WTHD values, i.e., THD(v B2C2 )=50.1% and WTHD(v B2C2 )=0.45%, respectively. As results, compared with the conventional PWM technique in faulty condition, the proposed technique advantageously reduce the harmonic distortion by 40% in terms of THD and by 94% in terms of WTHD, respectively. The simulated THD and WTHD characteristics of output voltages in SPWM technique under different operations are shown in Figure 11 and Figure 12, respectively. From Figure 11 and Figure 12, it can be seen that the aforementioned faulty condition leads to a considerably increasing in harmonic content of v BC compared with those of v AB and v CA , especially at low modulation indices. For instance, under normal operation with conventional PWM at m=0.5, the THD  technique are illustrated in the following figures from Figure 13 to Figure 17. The waveforms of output voltages and currents in Figure 13 corresponding to MOCBPWM technique are similar to those of SPWM technique shown inFigure 8. The experiment results in Figure 14 verify the simulation ones. In the simulation, THD and WTHD of v A3B2 are 36.4% and 0.28%, respectively while those in experiment are 37.1% and 0.57%, respectively. Similarly, with the 322-MOCBPWM algorithm, output voltages and currents in 322-type VSI are improved, as shown in Figure 15. As an example for m=0.8, Figure 15(a) and Figure 15(b) show significant increasing in harmonic distortion factor of v AB from THD(v A3B3 )=22.5% to THD(v A3B2_0 )=63.1%, and from WTHD(v A3B3 )=0.14% to WTHD(v A3B2_0 )=6.45% , respectively. However, results from Figure 15(c) show that the proposed 322-MOCBPWM technique reduces the THD and WTHD of v AB to 36.4% and 0.28%, respectively, i.e. a reduction of 42% as regards to THD and 96% as regards to WTHD. The fundamental voltage v AB which reduced from 80 V in normal operation to 61.2 V in faulty operation with conventional MOCBPWM, as shown in Figure 15(a) and Figure 15(b), is now recovered to the initial reference value, i.e., V A3B2(1) =80 V which shown in Figure 15(c). The effectiveness of 322-MOCBPWM technique on v BC and v CA can be observed in Figure 15, as well. The simulated THD and WTHD characteristics of output voltages in MOCBPWM technique are illustrated in Figure 16 and Figure 17, respectively. Characteristics shown in Figure 16 and Figure 17 have the similarity to those in Figure 11 and Figure 12 so that the faulty operation of 333-type VSI leads to a considerably surge in harmonic distortion of L2L voltages, especially in the low values of modulation index. In addition, the voltage v BC has the worst harmonic distortion compared to that of v AB and v CA , as regarding to the same value of m. For instance, under faulty condition for m=0.5, THD(v B2C2_0 )=285% while THD(v A3B2_0 )=194% and THD(v C2A3_0 )=170%. With use of the proposed 322-MOCBPWM technique, these values are 72%, 69%, and 64%, respectively. Therefore, there is only small difference between THD values of output voltages with the proposed algorithm. As regarding to WTHD factor, with use of compensating PWM algorithm, at m=1, they are WTHD(v A3B2 )=0.29%, WTHD(v B2C2 )=0.37%, and WTHD(v C2A3 )=0.37% while those values under faulty condition are 4.30%, 4.13%, and 3.58%, respectively.
In terms of v BC , simulated results in two CBPWM techniques with m=0.8 can be summarized by Table 3. Comparison between 322-SPWM technique and 322-MOCBPWM technique, it can be seen that the second one has the lower values of harmonic distortion factors. For instance, under faulty condition, the proposed 322-SPWM strategy has THD(v B2C2 ) value of 50.1% while that of 322-MOCBPWM strategy is 45.7%. The corresponding WTHD(v B2C2 ) of these algorithms are 0.45% and 0.36%, respectively. Hence, the harmonic distortion metrics of v BC in 322-MOCBPWM are lower than that in 322-SPWM by 8.8% in terms of THD and by 20% in terms of WTHD, respectively.

CONCLUSION
This paper has presented the analysis and implementation of CBPWM techniques on a 333-type VSI working under simultaneous SOC faults on two neutral-point-connected phase-legs. Simulation results show that under the aforementioned SOC fault condition, the output voltages and currents are strongly distorted and unbalanced, with a reduction of fundamental voltages by up to 30%. The use of the proposed 322-SPWM and 322-MOCBPWM techniques can help attaining required fundamental voltages, and also lowering harmonic content after faulty condition. For the worst harmonic quality voltage v BC , the proposed 322-SPWM has the ability in reduction of 40% and 94% in terms of THD and WTHD, respectively, while the corresponding results of 322-MOCBPWM technique are 42% and 96%, as regard to m=0.8. The advantages of 322-MOCBPWM technique compared to 322-SPWM technique are also presented, which are not only the extension of modulation range but also the better harmonic quality at the same operating condition. Compared with other studies cited, the proposed techniques do not need any additional hardware but still guarantees the desired values of fundamental voltages and balanced output currents. The proposed CBPWM algorithms are simple and easy for implementation, as well.